The present invention relates generally to integrated circuits and in particular the present invention relates to thermal processing for an improved CMP process.
As the density of semiconductor devices continues to increase, the need for smaller interconnections also increases. Historically, the semiconductor industry has used a subtractive etching process to pattern metal interconnect layers of the semiconductor. This metal processing technique, however, has limitations including poor step coverage, non-planarity, shorts and other fabrication problems. To address these problems, a dual damascene technique has been developed. This process, as explained in xe2x80x9cDual Damascene: A ULSI Wiring Technologyxe2x80x9d, Kaanta et al., 1991 VMIC Conference, 144-150 (Jun. 11-12, 1991) and incorporated herein by reference, involves the deposition of a metal into contact vias and conductor trenches which are patterned in the semiconductor. The semiconductor is then subjected to a known CMP (chemically-mechanically polish) process to both planarize the semiconductor and remove excess metal from all but the patterned areas.
The metal layer can be fabricated using known CVD (chemical vapor deposition) or PVD (physical vapor deposition) techniques. The metal interconnects are typically an aluminum alloys containing dopants, such as silicon and copper. These dopants are Si and Cu precipitates which tend to migrate to the grain boundaries of the aluminum during deposition. The precipitates are harder than aluminum. Thus, they are hard to dissolve and remove during the CMP process. The precipitates also contribute to defects in the aluminum, such as scratches, which materialize during the CMP process. These problems are present in all CMP processes, and not limited to removing metal alloys used in a dual damascene process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a process of fabricating metal alloy interconnects in an integrated circuit which improves a CMP process and reduces defects experienced during CMP.
The above-mentioned problems with integrated circuit fabrication and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A thermal processing method is described which improves metal polishing and increases conductivity following polish.
In particular, the present invention describes a method of fabricating a metal layer in an integrated circuit. The method comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution, and quenching the integrated circuit to prevent the alloy dopants from coming out of solution. Excess metal alloy is then removed using a polish process, and a second anneal is performed after the excess metal alloy is removed to allow the dopants to come out of solution and increase a conductivity of the metal alloy.
In another embodiment, a method of fabricating a metal layer in an integrated circuit. The method comprises the steps of forming vias and interconnect trenches in the integrated circuit and depositing a layer of metal alloy which contains alloy dopant precipitates on the integrated circuit to fill the vias and interconnect trenches. A first anneal of the integrated circuit at 400 to 500xc2x0 C. to drive the alloy dopants into solid solution. The integrated circuit is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy using a chemical-mechanical polish process. A second anneal at 150 to 250xc2x0 C. allows the dopants to come out of solution and increase a conductivity of the metal alloy.
A method of improving a chemical-mechanical polish (CMP) process in an integrated circuit is described. The method comprises the step of annealing the integrated circuit prior to performing the chemical-mechanical polish process to drive alloy dopants into solid solution.
A memory device is described which comprises an array of memory cells, internal circuitry, and metal contacts and interconnects coupled to the memory array and internal circuitry. The metal contacts and interconnects are formed by annealing the memory at a temperature sufficient to drive alloy dopants into solid solution prior to polishing the memory device to remove portions of a metal layer and form the metal contacts and interconnects.